Bipolar-CMOS-DMOS (BCD) process technology combines bipolar transistors, complementary metal-oxide-semiconductor (CMOS) devices and double diffused metal-oxide-semiconductor (DMOS) devices on a single chip. Bipolar devices are used for analog circuitry, CMOS devices are for logic circuitry and DMOS devices are for high voltage devices. The BCD device has advantages of high frequency and high power drive capability due to the bipolar transistors, low power consumption and high integration density due to the CMOS transistors, and excellent power controllability due to a low on-resistance between a drain and a source of each DMOS transistor and its large current and high breakdown voltage. Thus, BCD technology is often used for manufacturing high voltage power management integrated circuits or analog system-on-chip applications, with particular applications in wireless handheld electronics and consumer electronics.
Generally in BCD technologies, the highest operating voltage is limited by (1) reach-through breakdown of a vertical structure of P to N junction, (2) high voltage tub to p-substrate or ground and/or (3) other parameters. This vertical junction breakdown is a function of Epi thickness, doping concentration and junction depth. Thus, in addition to isolation of high voltage and low voltage devices, BCD technology requires an N-type stopper for having low voltage devices in a high voltage tub to prevent punch through. FIG. 1A shows an example of a BCD device 10 with conventional isolation and punch-through stopper configuration. The device 10 has an N-type epitaxial (N-epi) layer 14 disposed on a P-type substrate 12. Without showing the detailed structure of the device, a number of P-type regions (P-wells) 16 and 18 are provided in the N-epi layer 14. A dedicated mask is required to form a buried P-type regions 22 which extend from the bottoms of N-epi layer 14 upward into the bottom edge of P-wells 18 and merge together. Buried P-type regions 22 also extend downwards into the substrate 12, thus, providing isolation of the device 10 from the rest area of the semiconductor chip where other devices may be formed. Device 10 further comprises an N-type buried region 20 under the P-well 16 to prevent punch through between P-well 16 and P-type substrate 12 which limits the maximum operating voltage of the device 10. The N-type buried region 20 requires a dedicated mask to form in the process. Thus, the performance of device 10 may be optimized by using a certain thickness of N-epi layer 14 and controlling the depth of P-well 16 and the lateral distance between N-type buried region 20 and P-type buried region 22.
The manufacturing process would start with the substrate material 12 and ion implantation for regions 20 and 22 to be formed respectively in later steps. A dedicated zero mask is required by etching unused areas of the silicon to leave marks for alignment. The epitaxial layer 14 is then disposed on top of the substrate material 12 and multiple N-wells and P-wells are formed extending downwards from the top surface of the epitaxial layer. Additional steps may be carried out to form a specific function such as a bipolar transistor or a MOSFET. It is noted that a P-Epi layer may be used instead of N-Epi layer, but it requires an additional lightly doped N-well region deep enough to convert P- to N-. N Epi can form N-tub by only P-Iso.
Alternatively, a blanket implantation may be carried out to form a P-type buried layer 22a on top of the P-type substrate 12a as shown in FIG. 1B. In addition, P-well isolation regions 18a have to be deep enough to reach the P-type buried layer 22a. With this configuration, one less mask is used. While the configuration of FIG. 1B is good enough for the device with a relatively low operating voltage, e.g., less than 40 volts, the configuration of FIG. 1A is usually used when the device has a much higher operating voltage, e.g., 100 V or more.
Fabrication of the BCD device may need complex process technologies and a large number of photo masks. Forming the N-type buried region 20 and P-type buried layer 22 and lightly doped deep N-well regions (not shown) used to form N tubs requires high temperature long duration diffusion cycles. Furthermore, the epitaxy step is expensive. Therefore conventional BCD process flow is long and is expensive. Thus, manufacturing costs of the BCD device may be increased. Therefore, various process technologies for forming the BCD device may still be required to reduce the manufacturing costs and to improve performance thereof.
It is within this context that embodiments of the present invention arise.